1. Field of the Invention
The present invention relates generally to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device with different spacer thickness. The thickness of the spacer is adjusted according to the desired spacing between the strained silicon structure and the gate structure.
2. Description of the Prior Art
Recent advances in semiconductor technology as applied to integrated circuits include the use of “strain engineering” (or, alternatively, “stress engineering”) in the manufacture of semiconductor device structures. It has been discovered that the tuning of strain in the crystal lattice of metal-oxide-semiconductor (MOS) transistor channel regions can enhance carrier mobility in those regions. As is fundamental in MOS device technology, the source/drain current (i.e., drive) of an MOS transistor in both the triode and saturation regions is proportional to carrier mobility in the channel region. In a general sense, compressive stress enhances hole mobility in the channel region of a p-channel MOS transistor, and tensile stress enhances electron mobility in the channel region of an n-channel MOS transistor. Typically, p-channel MOS transistors exhibit lower drive capability than n-channel MOS transistors in typical modern integrated circuits. As such, strain engineering techniques are more typically applied to p-channel MOS transistors than to n-channel MOS transistors in current day manufacturing technology.
Various strain engineering approaches are known in the art. According to the approach known as “embedded SiGe” (also referred to as “eSiGe”), the source and drain regions of a p-channel MOS transistor structure are etched from the silicon substrate or well region, and are replaced with a silicon-germanium alloy formed by selective epitaxy. Because of the germanium atoms within the crystal lattice, the germanium constituting as much as 25% to 30% (atomic) of the alloy, eSiGe exhibits a larger lattice constant than does silicon (i.e., the distance between unit cells in the crystal lattice for SiGe is greater than in single-crystal silicon). Embedded eSiGe source/drain regions thus apply compressive stress to the channel region of the p-channel MOS transistor being formed. This compressive stress in the channel increases the hole mobility of the p-channel MOS transistor, and enhances its performance.
A similar approach for improving carrier mobility is known for n-channel MOS transistors. Commonly assigned U.S. Pat. No. 7,023,018, incorporated herein by reference, describes the use of silicon-carbon alloy material as source/drain structures in n-channel MOS transistors. As described in that U.S. patent, silicon-carbon source/drain structures cause an increase in tensile stress in a direction parallel to the intended direction of source/drain current flow in the transistor. This tensile stress in the source/drain regions increases tensile strain in the p-type channel region between the source and drain structures, which increases electron mobility in that channel region and thus improves the performance of the n-channel MOS transistor.
It has been observed, however, that the physical shape of the strained eSiGe can be quite non-uniform within an integrated circuit due to loading effects from neighboring geometries. This issue is mainly resulted from the varied width and poly/feature spacing of devices in different pattern density or layout. The non-uniform shapes of strained eSiGe would affect device's performance since the eSiGe overfill and the resulting strain force exerts on the lattice in the channel would vary from the different devices.
One could avoid this undesired effect in several conventional ways. One approach would be to design the gate structures with a relatively constant width and spacing across the integrated circuit; however, this constraint would significantly reduce the ability of the designer to optimize the layout for device and circuit performance. Another approach would be to incorporate sacrificial “dummy” structures, such that the loading effects would be absorbed by non-functional structures. Of course, that approach consumes valuable chip area. It would be necessary for those ordinarily skilled in the art to find a better solution.